1. Field of the Invention
The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and a method of coupling semiconductor devices.
2. Description of the Related Art
For integrated circuits (IC), there is a need for additional input, output, and power connections. More specifically, where two semiconductor devices are positioned face to face with the I/O pads on the two devices aligned in the x and y directions and as near as possible in the z direction, a technical problem arises when aligning the two devices constructed using typical IC planar fabrication techniques so that critical features (the I/O signal and power pads) of the two chips are in proximity to each other. It is desirable for the alignment to be reliable, inexpensive, and accurate. In addition, the alignment should be maintainable during long-term operation. Improved accuracy in the pad alignment and reduced pad separation in the z direction would allow for a reduction in the size and pitch of pads and an increase in the total number of chip pads. Accordingly, there is a need for an improved multi-chip semiconductor device and method of coupling semiconductors.
The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.
In another embodiment, the multi-chip semiconductor device comprises a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device has a first surface, the first surface containing a first plurality of pads, the first surface forming a first alignment pattern. The second semiconductor device has a second surface, the second surface containing a second plurality of pads and forming a second alignment pattern. The third semiconductor device has a third surface forming a third alignment pattern. The third alignment pattern complements the first and second alignment patterns of the first and second semiconductor devices.
In another embodiment, a method of coupling a first semiconductor device and a second semiconductor device is described. The method comprises providing the first and the second semiconductor device, the first semiconductor device including a first patterned surface, the first patterned surface supporting a first plurality of circuit pads, the second semiconductor device including a second patterned surface, the second patterned surface supporting a second plurality of circuit pads; aligning the second semiconductor device with respect to the first semiconductor device such that the first patterned surface opposes the second patterned surface, wherein the first patterned surface is substantially parallel to the second patterned surface and the first patterned surface is oriented such that the first plurality of circuit pads are proximate to corresponding pads of the second plurality of circuit pads; and positioning the second semiconductor device and the first semiconductor device closer together such that the first plurality of circuit pads are capacitively coupled to the second plurality of circuit pads.
In another embodiment, the multi-chip semiconductor device comprises a first semiconductor device having a first surface, the first surface containing a first alignment region on a portion of the first surface, the first alignment region including a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members; and a second semiconductor device having a second surface, the second surface containing a second alignment region on a portion of the second surface, the second alignment region including a third ridge alignment member, the second semiconductor device positioned such that the second alignment region opposes the first alignment region and such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.
In another embodiment, the semiconductor device comprises an integrated circuit device having a first surface supporting a plurality of pad elements and a plurality of circuit elements, the first surface containing a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members, the receiving area formed to receive a third alignment member of a second integrated circuit device when the second integrated circuit device opposes and is substantially aligned with the integrated circuit device.